Self-synchronous transfer control circuit and data driven information processing device using the same

ABSTRACT

When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the self-synchronous transfer control circuit, when a data transfer enabling signal is applied from a C element in a subsequent stage, a node number manipulation circuit manipulates a node number to make copies such that packets can be distinguished from each other, and then data is transferred from a pipeline register to a pipeline register in a subsequent stage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a self-synchronous transfer controlcircuit and a data driven information processing device using the same,and more particularly, to a data driven information processing device inwhich a self-synchronous transfer control circuit enabling transfer of aplurality of pulses from one pulse is used for multi-outputinstructions, to enhance program performance.

2. Description of the Background Art

As the use of multimedia has been increased in recent years, a largeamount of operations are required in image processing and so forth. Thedata driven information processing device (hereinafter referred to as adata driven processor) has been proposed as a device for rapidlyprocessing such a large amount of operations. In the data drivenprocessor, a process is carried out according to a rule in that theprocess is performed when there are all the input data required for aprocess and a resource required for the process such as an operationdevice is allocated. A data transmission device employing anasynchronous handshake system is used for a data processing deviceincluding information processing operation of the data driven type. Insuch a data transmission device, a plurality of data transmission pathsare connected with each other, which mutually transmit/receive datatransfer request signals (hereinafter referred to as SEND signal) andtransfer enabling signals indicating whether or not the data transfer ispermitted (hereinafter referred to as ACK signal), to autonomouslytransfer data.

FIG. 12 shows a format of a data packet to which a conventional art andthe present invention are applied. In FIG. 12, the data packet includesa destination node number area F1 for storing a destination node numberND#, a generation number area F2 for storing a generation number GN#, aninstruction code area F3 for storing an instruction code OPC and a dataarea F4 for storing data DATA. The generation number herein represents anumber for distinguishing data groups to be subjected to parallelprocessing from each other. The destination node number represents anumber for distinguishing input data within one generation from eachother. The instruction code is for executing instructions stored in aninstruction decoder.

FIG. 13 is a block diagram showing a configuration of a datatransmission path. The data transmission path includes aself-synchronous transfer control circuit (hereinafter referred to as aC element) 1 a and a data holding circuit (hereinafter referred to as apipeline register) 1 b constituted by a D type flip-flop. C element 1 aincludes a pulse input terminal CI receiving a pulse, a transferenabling output terminal RO outputting a transfer enabling signalindicating enabling or disabling of the transfer, a pulse outputterminal CO outputting a pulse, a transfer enabling input terminal RIreceiving the transfer enabling signal indicating enabling or disablingof transfer, and a pulse output terminal CP for applying a clock pulsecontrolling the data holding operation of pipeline register 1 b.

FIGS. 14A to 14E are timing charts illustrating the operation of Celement shown in FIG. 13. When C element 1 a receives a pulse indicatedin FIG. 14A from terminal CI, if the transfer enabling signal input atterminal RI shown in FIG. 14E is enabled, C element outputs a pulseindicated in FIG. 14D from terminal CO and also outputs a pulse shown inFIG. 14C to pipeline register 1 b. In response to the pulse applied fromC element 1 a, pipeline register 1 b holds the applied input packetdata, and then outputs the held data as output packet data.

FIG. 15 is a block diagram showing an example where the datatransmission paths shown in FIG. 13 are connected in sequence viapredetermined logic circuits. The input packet data is processedsequentially in logic circuits 3 d and 3 e while sequentially beingtransferred along pipeline registers 3 a→3 b→3 c. In FIG. 15, forexample, when pipeline register 3 a is in a data holding state whilepipeline register 3 b in the subsequent stage is also in the dataholding state, no data is transmitted from pipeline register 3 a topipeline register 3 b.

Further, if pipeline register 3 b in the subsequent stage is in non-dataholding state or has come to be in the non-data holding state, data istransmitted from pipeline register 3 a to logic circuit 3 d, where thedata is processed, and to pipeline register 3 b, taking at least apreset delay time. A control which is called a self-synchronous transfercontrol asynchronously transmits data with at least preset delay time,in response to SEND signals input to/output from terminals CI and CO andACK signals input to/output from terminals RI and RO, which aretransmitted between adjacent pipeline registers connected as describedabove. A circuit controlling such data transfer is called aself-synchronous transfer control circuit.

FIG. 16 is a detailed circuit diagram of the C element shown in FIG. 15.The C element may be, for example, the one described in Japanese PatentLaying-Open No. 6-83731. In FIG. 16, pulse input terminal CI receives apulsed SEND signal (a transfer request signal) from a preceding stage,and transfer enabling output terminal RO outputs an ACK signal (atransfer enabling signal) to the preceding stage. Pulse output terminalCO outputs a pulsed SEND signal to a subsequent stage, and transferenabling input terminal RI receives an ACK signal from the subsequentstage.

A master reset input terminal MR receives a master reset signal. When apulse at a logic high or “H” level is applied to master reset inputterminal MR, the pulse is inverted at an inverter 4 e, and the invertedpulse resets flip-flops 4 a and 4 b to initialize C element. Then, an“H” level signal is output, as an initial state, from both pulse outputterminal CO and transfer enabling output terminal RO. The “H” leveloutput from transfer enabling output terminal RO indicates a transferenabling state, whereas a logic low or an “L” level output therefromindicates a transfer disabling state. Further, the “H” level output frompulse output terminal CO indicates the state where no data transfer isrequired for the subsequent stage, whereas the “L” level therefromindicates a state where the data transfer is required for or the data isbeing transferred to the subsequent stage.

When the signal of “L” level is input to pulse input terminal CI, i.e.,when data transfer is required from the preceding stage, flip-flop 4 ais set and outputs an “H” level signal to an output Q. The “H” levelsignal is inverted at an inverter 4 d, and thus an “L” level signal isoutput from transfer enabling output terminal RO, which inhibits furtherdata transfer. After a certain period of time, an “H” level signal isinput to pulse input terminal CI, terminating data setting from thepreceding stage to the C element. In such a state, when the circuit isin a state where an “H” level signal is input from transfer enablinginput terminal RI, i.e. where the data transfer from the subsequentstage is permitted, and also in a state where pulse output terminal COis outputting no “H” level signal, i.e., is transferring no data to thesubsequent stage (the state where no data transfer is required for thesubsequent stage), an NAND gate 4 c is activated, outputting an “L”level signal.

As a result, flip-flops 4 a and 4 b are both reset, and flip-flop 4 boutputs an “H” level signal, via a delay element 4 e, from pulse outputterminal CP to the pipeline register, together with a SEND signal of the“L” level, via a delay element 4 f, from pulse output terminal CO to theC element in the subsequent stage. That is, the data transfer for thesubsequent stage is required. The C element in the subsequent stagewhich has received the SEND signal of the “L” level outputs an ACKsignal made to be at “L” level from terminal RO, indicating transferinhibition, such that no further data is transferred to the C element.The C element inputs the “L” level ACK signal from transfer enablinginput terminal RI, setting flip-flop 4 b. As a result, the “L” levelsignal is output, via delay element 4 e, from pulse output terminal CPto the pipeline register, and also the “H” level SEND signal is output,via delay element 4 f, from pulse output transmit CO to the subsequentstage, terminating the data transfer.

FIG. 17 is a schematic block diagram of a conventional data drivenprocessor configured including the data transfer device shown in FIG.15. In FIG. 17, a data driven processor Pe includes a junction unit JNC,a firing control unit FC, an operation unit FP, a program storage unitPS, a branch unit BRN, a plurality of pipeline registers 3 a to 3 c, anda plurality of C elements 2 a to 2 c. Each of C elements 2 a to 2 ccontrols packet transfer for a corresponding processing unit (FC, FP orPS) by exchanging packet transfer pulses (signals at CI, CO, RI and RO)to C elements in preceding and subsequent stages. In response to pulseinputs from the corresponding C elements 2 a to 2 c, pipeline registers3 a to 3 c each takes in the data input from the preceding processingunit and holds the data, and delivers it to the output stage, where thedata is held until the next pulse is input.

In FIG. 17, when the data packet shown in FIG. 12 is input to processorPe, the input packet first passes through junction unit JNC, istransferred to firing control unit FC, and a pair data is formed fromidentical packets based on a destination node number ND# and ageneration number GN#. That is, two different data packets havingidentical node number ND# and generation number GN# are detected, andthe data in one of the data packets is additionally stored in data areaF4 (FIG. 12) of the other data packet, outputting the other data packet.The packet of which the pair data (a set of data) is stored in data areaF4 is subsequently transmitted to operation unit FP. Operation unit FPinputs the transmitted data packet, executes a predetermined operationfor the content of the input packet based on instruction code OPC of theinput packet, and stores the operation result in data area F4 of theinput packet. The input packet is subsequently transmitted to programstorage unit PS.

Program storage unit PS inputs the transmitted data packet, and readsnode information (node number ND#) to which the packet should go nextfrom the program memory in program storage unit PS, instructioninformation (instruction code OPC) to be subsequently executed, and acopy flag CPY. The read destination node number ND# and instruction codeOPC are then stored respectively in destination node number area F1 andinstruction code area F3 of the input packet. Further, if the read copyflag CPY is “I”, the subsequent address in the program memory isdetermined also to be valid, and thus the packet storing destinationnode number ND# and instruction code OPC stored in the next address willalso be generated.

The packet output from program storage unit PS is transmitted to branchunit BRN, and is output based on its destination node number ND#, or isreturned again into the processor. To make three copies of identicaldata, the packet returned to the processor will be used for the copyingprocess. Thus, to make a plurality copies of the identical data, thepacket must be returned to the processor a plurality of times for thecopying process.

FIG. 4A is a data flow diagram showing an example where four copies ofthe input data are made. An NOP (copying without operation) instruction16 a is executed for the input data to output data 16 h and 16 i. Data16 i is executed as an OPC1 instruction 16 d corresponding toinstruction code OPC of the packet shown in FIG. 12, and data 16 h isexecuted as an NOP instruction 16 b. In NOP instruction 16 b, copying isexecuted to output data 16 j and 16 k. Data 16 k is executed as an OPC2instruction 16 e, and data 16 j is executed as an NOP instruction 16 c.In NOP instruction 16 c, copying is executed to output data 16 l and 16m. Data 16 m is executed as an OPC3 instruction 16 f, and data 16 l isexecuted as an OPC4 instruction 16 g. Thus, to make four copies of data,two packet-copying instructions must be executed three times.

FIG. 18 is a diagram showing an example where a conventional data drivenprocessor is used to execute a multiplication instruction. In FIG. 18, amultiplier 3 f and a shifter 3 g are provided as logic circuits 3 d and3 e shown in FIG. 15 described earlier. For example, 12-bit data ismultiplied with another 12-bit data, the operation result will be 24-bitdata. However, the data to be stored in the data field as a packetformat is limited to 12 bits as shown in FIG. 12, and therefore theresulted data of 24 bits must be divided into higher 12 bits and lower12 bits for operation. Thus, shifter 3 g has been used to execute twoinstructions, such as an instruction outputting a packet including thehigher 12-bit data and an instruction outputting a packet including thelower 12-bit data, to realize the operation. As described above, when aprocess is to be executed such that a plurality of copies of packets aremade or a plurality of identical data are required in the conventionaldata driven processor, it can be realized by executing the NOPinstruction a plurality times, which however generates a uselessgo-around packet for executing the NOP instruction, i.e. a go-aroundpacket returned from the packet output to the packet input as shown inFIG. 17. This has made it difficult to enhance the performance of theprogram execution.

SUMMARY OF THE INVENTION

A main object of the present invention is, therefore, to provide aself-synchronous transfer control circuit for enabling efficientexecution of a program, and a data driven information processing deviceusing the same.

According to one aspect of the present invention, a self-synchronoustransfer control circuit includes: a transfer control circuittransferring a first pulse applied from a preceding stage to asubsequent stage as a second pule based on an instruction signalinstructing enabling or disabling of transfer; and a pulse controlcircuit receiving one data transfer request pulse signal as the firstpulse from the transfer control circuit in the preceding stage to outputa plurality of data transfer request pulse signals as the second pulseto the transfer control circuit in the subsequent stage.

Thus, according to the present invention, it is possible to receive onedata transfer request pulse signal from the transfer control circuit inthe preceding stage to output a plurality of data request pulse signalsto the transfer control circuit in the subsequent stage, enablingseveral-fold efficient data transfer control compared to a conventionalexample.

Preferably, a data number setting circuit is further provided, which canset the number of data transferred to the transfer control circuit inthe subsequent stage.

Preferably, the pulse control circuit includes: a first logic circuitoutputting a transfer enabling pulse signal to the transfer controlcircuit in the preceding stage as a third pulse, in response toapplication of the data transfer request pulse signal from the transfercontrol circuit in the preceding stage; a second logic circuitoutputting data transfer request pulse signal to the transfer controlcircuit in the subsequent stage; a storage circuit storing the number ofdata in response to setting of the number of data by the data numbersetting circuit; a gate circuit receiving a transfer enabling signal asa fourth pulse from the transfer control circuit in the subsequentstage; and a transfer circuit outputting the transfer request pulsesignal from the second logic circuit by the number of data stored in thestorage circuit every time the gate circuit receives the transferenabling signal, in response to application of the data transfer requestpulse signal to the first logic circuit, when the number of data isstored in the storage circuit.

More preferably, the pulse control circuit includes: a counter circuitcounting the number of times the transfer request pulse signal isoutput; and a disabling circuit comparing the counter output of thecounter circuit with the number of data stored in the storage circuit todisable the output of the transfer request pulse signal by the transfercircuit, in response to correspondence thereof.

According to another aspect of the present invention, a data driveninformation processing device, using a self-synchronous transfer controlcircuit receiving one data transfer request pulse signal indicatingrequest of transfer from a transfer control circuit in a preceding stageto output a plurality of transfer request pulse signals to a transfercontrol circuit in a subsequent stage, includes: a data transmissionpath holding a data packet based on a clock signal applied from theself-synchronous transfer control circuit; and a data number detectioncircuit for detecting the number of data based on output packetinformation set to the data packet held in the data transmission path,the self-synchronous transfer control circuit outputting a transferrequest pulse signal corresponding to the number of data, in response todetection of the number of data by the data number detection circuit.

Preferably, the data transmission path holds a data packet including adestination field storing at least destination information, aninstruction field storing instruction information and a data fieldstoring data, and the data number detection circuit transmits, inresponse to detection that a copying instruction is present in aninstruction field included in the data packet held in the datatransmission path, data copied from the data transmission path to a datatransmission path in a subsequent stage.

More preferably, the data number detection circuit transmits a pluralityof data packets having the same data as the data in a data fieldincluded in the data packet and having destination information differentfrom each other, from the data transmission path to a data transmissionpath in a subsequent stage, in response to detection of the copyinginstruction.

More preferably, the data number detection circuit transmits a pluralityof data packets different from data in the data packet from the datatransmission path to a data transmission path in a subsequent stage, inresponse to detection of the copying instruction.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a self-synchronous transfer controlcircuit used in a data driven processor according to the firstembodiment of the present invention;

FIGS. 2A to 2J are timing charts illustrating the operation of theself-synchronous transfer control circuit shown in FIG. 1;

FIG. 3 is a block diagram illustrating a process procedure for making Ncopies of an input data, according to the second embodiment of thepresent invention;

FIGS. 4A and 4B are flow diagrams contrastively showing processprocedures making four copies of the input data, according to aconventional example and to the second embodiment of the presentinvention;

FIG. 5 is a block diagram showing a process content of a multiplicationinstruction in relation to a multiplication process causing an overflow,according to the third embodiment of the present invention;

FIG. 6 is a detailed circuit diagram of the self-synchronous transfercontrol circuit shown in FIG. 5;

FIGS. 7A to 7H are timing charts illustrating the operation of theself-synchronous transfer control circuit shown in FIG. 6;

FIGS. 8A and 8B are flow diagrams contrastively showing themultiplication process causing the overflow, according to a conventionalexample and to the third embodiment of the present invention;

FIG. 9 is a block diagram illustrating a procedure simultaneouslyprocessing three data, according to the fourth embodiment of the presentinvention;

FIG. 10 is a detailed circuit diagram of the self-synchronous transfercontrol circuit shown in FIG. 9;

FIGS. 11A to 11J are timing charts illustrating the operation of theself-synchronous transfer control circuit shown in FIG. 10;

FIG. 12 shows a format of a data packet applied to a conventionalexample and an embodiment of the present invention;

FIG. 13 shows a data transmission path in a conventional data drivenprocessor;

FIGS. 14A to 14E are timing charts showing the operation of the Celement shown in FIG. 13;

FIG. 15 is a block diagram showing a conventional general data drivendevice;

FIG. 16 is a circuit diagram showing a conventional C element;

FIG. 17 is a block diagram showing a conventional data driven processor;and

FIG. 18 shows an example where a multiplication instruction is executedin a conventional data driven processor.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a circuit diagram showing a self-synchronous transfer controlcircuit in the first embodiment of the present invention. In FIG. 1, apulse input terminal CI receives a pulsed transfer request signal from apreceding stage, and a transfer enabling output terminal RO outputs atransfer enabling signal to the preceding stage. A pulse output terminalCO outputs a pulsed transfer request signal to a subsequent stage, and atransfer enabling input terminal RI receives a transfer enabling signalfrom the subsequent stage. A master reset input terminal MRB receives amaster reset signal, and a terminal EXB receives a packet erasingsignal. A terminal CPY receives a packet copying signal, and an terminalNUM receives a packet copying number signal.

Further, the self-synchronous transfer control circuit includes Celements 9 a and 9 b, D type flip-flops 9 c, 9 d, 9 e and 9 g, NANDgates 9 k and 9 i, OR gates 9 l and 9 n, AND gates 9 p, 9 j and 9 m, acounter 9 f, inverters 9 h, 9 q, 9 r, 9 u and 9 v, a flip-flop 9 s, anda delay element 9 t.

FIGS. 2A to 2J are timing charts illustrating the operation of theself-synchronous transfer control circuit shown in FIG. 1.

Subsequently, referring to the timing charts in FIGS. 2A to 2J, a packeterasing operation, a packet normal transfer operation and a packetcopying operation of the self-synchronous transfer control circuit inFIG. 1 are sequentially described.

First, when a pulse of “L” level is input from master reset terminalMRB, C elements 9 a and 9 b are reset, and “H” level signals are outputboth from the respective pulse output terminal CO and transfer enablingoutput terminal RO. The timing charts shown in FIGS. 2A to 2J begin fromthis state. As a result, as shown in FIGS. 2I and 2B, the “H” levelsignals are output both from pulse output terminal CO and transferenabling output terminal RO of the self-synchronous transfer controlcircuit, initializing the self-synchronous transfer control circuit.

Further, D type flip-flop 9 g is asynchronously reset, outputting an “L”level signal at its output Q. The signal is inverted to an “H” levelsignal at inverter 9 q, and is input to a three-input AND gate 9 m. Inthe operation of C elements 9 a and 9 b, parts overlapping with thosedescribed in the conventional art will not be repeated.

When the “L” level signal indicated in FIG. 2C is input to terminal EXB,the self-synchronous transfer control circuit executes the packeterasing operation. That is, when a pulse signal of the “L” level shownin FIG. 2A is input from pulse input terminal CI of the self-synchronoustransfer control circuit in a state where the “L” level signal has beeninput to terminal EXB, the pulse signal of the “L” level is input topulse input terminal CI of C element 9 a.

As for terminal RI, to which master reset signal MRB has already beeninput, the “H” level signal indicated in FIG. 2J is input thereto, and Celement 9 a operates as conventional. When terminal CI is raised to the“H” level as shown in FIG. 2A after a certain time period, the “L” levelsignal indicated in FIG. 2I is output from pulse output terminal CO of Celement 9 a, changing the level of the signal at pulse output terminalCP for a pipeline register to “H” level. The “H” level signal outputfrom terminal CP of C element 9 a sets flip-flop 9 s, which outputs the“L” level signal indicated in FIG. 2H to terminal FEB via delay element9 t.

Moreover, in synchronization with the rise of the signal at the terminalCP, D type flip-flop 9 c takes in the “L” level signal which has beeninput from terminal EXB, and takes out the signal from output Q thereof.This allows NAND gate 9 k to output an “H” level signal. Terminal CO ofC element 9 b also outputs an “H” level signal in a similar manner, andhence pulse output terminal CO of the self-synchronous transfer controlcircuit keeps outputting the “H” level signal via AND gate 9 p. Further,output Q of D type flip-flop 9 c is input to one input terminal of ORgate 9 l as an “L” level signal, so that the signal output from pulseoutput terminal CO of C element 9 a will directly be an output of ORgate 9 l.

Furthermore, an “H” level signal is applied to transfer enabling inputterminal RI of the self-synchronous transfer control circuit as aninitial state, so that the output signal of OR gate 9 l input to ANDgate 9 m will directly be an output signal of AND gate 9 m. As a result,the signal output from pulse output terminal CO of C element 9 a will beinput to transfer enabling input terminal RI of C element 9 a as it is.

As described above, the “L” level signal is output from pulse outputterminal CO of C element 9 a, and thus the “L” level signal is input totransfer enabling input terminal RI of C element 9 a. This changesterminal CP of C element 9 a to the “L” level as indicated also in thetiming charts of FIG. 14 referenced in the conventional example. As aresult, terminal CO of C element 9 a is changed to the “H” level, thesignal therefrom being input to terminal RI of C element 9 a via OR gate9 l and AND gate 9 m, which generates a state where subsequent datatransfer is permitted, terminating the packet erasing operation.

It is noted that, as clearly shown in FIG. 2, terminal CO is maintainedat the “H” level during the erasing operation, and thus the packet willnot be transferred to the subsequent stage, but be overwritten by thenext packet transferred from the preceding stage and disappears.

The packet normal transfer operation of the self-synchronous transfercontrol circuit will now be described. In a state where an “H” levelsignal is input from terminal EXB and an “L” level signal is input fromterminal CPY, when a pulse signal of “L” level is input from pulse inputterminal CI of the self-synchronous transfer control circuit, a pulsesignal of “L” level is input to pulse input terminal CI of C element 9a, C element 9 a operating as in the conventional example, and when thesignal at terminal CI is raised to “H” level after a certain period oftime, a “L” level signal is output from pulse output terminal CO of Celement 9 a. Further, a signal of the “H” level is output from pulseoutput terminal CP to the pipeline register. The “H” level signal frompulse output terminal CP of C element 9 a sets flip-flop 9 s, outputtingan “L” level signal to terminal FEB via delay element 9 t.

Moreover, in synchronization with the rise of the signal at pulse outputterminal CP, D type flip-flop 9 c takes in the “H” level signal whichhas been input from terminal EXB and delivers the signal to output Q ofD type flip-flop 9 c. Further, D type flip-flop 9 d takes in the “L”level signal indicated in FIG. 2D that has been input from terminal CPYat the same timing, and delivers the signal to output Q of D typeflip-flop 9 d. The “L” level signal output from D type flip-flop 9 d isinput to NAND gate 9 i, raising the output of NAND gate 9 i to “H”level. Also, because terminal CO of C element 9 b is at the “H” level inthe initial state, the output of OR gate 9 n and therefore of AND gate 9j will be at the “H” level. Pulse input terminal CI of C element 9 bkeeps receiving this “H” level signal, which prevents C element 9 b fromoperating in this mode.

The output signal of the “H” level from D type flip-flop 9 c is input toNAND gate 9 k, so that the output of NAND gate 9 k will output aninversion signal of the signal output from inverter 9 h, i.e. a signalidentical to the output of terminal CO of C element 9 a. Further,terminal CO of C element 9 b is fixed to “H” level, so that the signaloutput from NAND gate 9 k is input to NAND gate 9 p and is output fromNAND gate 9 p as it is. That is, a signal identical to the output signalof terminal CO of C element 9 a will be output from terminal CO of theself-synchronous transfer control circuit. The output signal of “H”level from D type flip-flop 9 c is also input to OR gate 9 l, fixing theoutput of OR gate to the “H” level.

Furthermore, D type flip-flop 9 g maintains the state where master resetsignal MRB is input, so that output Q thereof will be at the “L” leveland the output of inverter 9 q will be at the “H” level, and hence theoutput of AND gate 9 m will be a signal identical to the signal inputfrom terminal RI of the self-synchronous transfer control circuit. Thismeans that a signal identical to the signal input from terminal RI ofthe self-synchronous transfer control circuit will be input to terminalRI of C element 9 a. When terminal CP of C element 9 a described aboveis changed to the “H” level, the terminal CO of C element 9 a is changedto “L” level to be output, resulting that an “L” level signal is outputfrom terminal CO of the self-synchronous transfer control circuit.

After a certain time period, the “L” level signal is input from terminalRI of the self-synchronous transfer control circuit, and thus the “L”level signal is input to terminal RI of C element 9 a. This changes thesignal at terminal CP of C element 9 a to “L” level for being output,changing the signal at terminal CO of the C element 9 a, i.e. the outputfrom terminal CO of the self-synchronous transfer control circuit, to“H” level. The “H” level signal is then input from terminal RI of theself-synchronous transfer control circuit after a certain time period,generating a state where the subsequent data transfer is permitted, andthus the packet normal transfer operation of the self-synchronoustransfer control circuit is terminated.

Finally, the packet copying operation of the self-synchronous transfercontrol circuit will be described. An “H” level signal is input fromterminal EXB, an “H” level signal is input from terminal CPY, and packetcopying number information is input from terminal NUM. In this state,when a pulse signal of “L” level is input from pulse input terminal CIof the self-synchronous transfer control circuit, a pulse signal of “L”level is input to pulse input terminal CI of C element 9 a, C element 9a operating as in the conventional example. When terminal CI is raisedto “H” level after a certain period of time, a signal of “L” level isoutput from pulse output terminal CO of C element 9 a.

Further, the signal level at pulse output terminal CP for the pipelineregister is changed from “L” to “H” for being output. The signal of “H”level from terminal CP of C element 9 a sets flip-flop 9 s, outputtingan “L” level signal to terminal FEB of counter 9 f via delay element 9t.

Further, in synchronization with the rise of the signal at terminal CP,D type flip-flop 9 c takes in the “H” level signal which has been inputfrom terminal EXB and outputs the signal from output Q thereof.

Moreover, D type flip-flop 9 d takes in the “H” level signal which hasbeen input from terminal CPY at the same timing and takes out the signalat output Q of D type flip-flop 9 d, whereas D type flip-flop 9 e takesin an integer indicating the copying number information that has beeninput from terminal NUM at the same timing, as shown in FIG. 2E, andtakes out the signal from output Q of the same D type flip-flop 9 e. Dtype flip-flop 9 e shown in FIG. 1 is constituted by a plurality of Dtype flip-flops aligned in parallel, and when, for example, the copyingnumber information is five, three-bit information of “101” is inputusing three D type flip-flops for each bit.

Counter 9 f takes in the output of delay element 9 t, i.e. the output ofD type flip-flop 9 e indicating the copying number information when theFEB signal is at “L” level, and when the FEB signal is subsequentlyraised to “H” level, counter 9 f executes counting every time a clock isinput to terminal CK, outputs the counted value from terminal N toterminal NO, and outputs an “L” level signal from terminal Z. When thecounted value corresponds to the number set from terminal NUM, counter 9f stops the counting, which makes the output of terminal Z “H” level.

Terminal CP of C element 9 a is changed to “H” level, and thus theoutput of terminal CO of C element 9 a is changed to “L” level, thesignal being input to inverter 9 h, which outputs an “H” level signal.The “H” level signal at the output of inverter 9 h is input to NAND gate9 k, and also an “H” level signal is input to the other input terminalfrom output Q of D type flip-flop 9 c, so that the output of NAND gate 9k will be at “L” level. The “L” level signal is input to AND gate 9 p,which therefore outputs the “L” level signal. That is, theself-synchronous transfer control circuit outputs the “L” level signalfrom terminal CO. Then, after a certain period of time, the “L” levelsignal will be input from terminal RI of the self-synchronous transfercontrol circuit.

The “H” level signal at the output of inverter 9 h is also input to NANDgate 9 i. Further, D type flip-flops 9 c and 9 d both output “H” levelsignals, which makes the output of NAND gate 9 i “L” level. The “L”level signal is input to AND gate 9 j, outputting the “L” level signal,which will be applied to pulse input terminal CI of C element 9 b. Thischanges the signal level at transmission enabling output terminal RO ofC element 9 b to “L” level for being output, and the signal is input toset terminal S of D type flip-flop 9 g to asynchronously set the same,resulting that an “H” level signal is output from output Q of D typeflip-flop 9 g. The “H” level signal is input to inverter 9 q, the outputthereof being “L” level. The “L” level signal is input to AND gate 9 m.

The “L” level signal input from terminal RI of the self-synchronoustransfer control circuit is input to AND gate 9 m. The output of ANDgate 9 m will be at “L” level, and the “L” level signal will then beinput to terminal RI of C element 9 a. This changes the signal level atterminal CP of C element 9 a to “L” for being output, and changes thesignal level of terminal CO of C element 9 a to “H” to the contrary.

Further, when the “L” level signal input from terminal RI of theself-synchronous transfer control circuit is input to terminal RI of Celement 9 b, terminal CO of C element 9 b is changed to “H” level. Whenthe “H” level signal is output from terminal CO of C element 9 a, the“H” level signal is applied to AND gate 9 p via inverter 9 h and NANDgate 9 k. Because terminal CO of C element 9 b is at “H” level, the “H”level signal is output from AND gate 9 p to terminal CO of theself-synchronous transfer control circuit.

After a predetermined period of time, terminal RI of theself-synchronous transfer control circuit is changed from “L” level to“H” level for being input, terminating the transfer of the first packet.At that time, an “L” level signal is output from terminal FEB, and theoutput from terminal NO will be indeterminate, since counter 9 f is notoperating.

Whereas, the “H” level signal output from terminal CO of C element 9 ais separately applied to AND gate 9 j via inverter 9 h and NAND gate 9i. At this time point, terminal CO of C element 9 b is at “H” level,making the output of OR gate 9 n the “H” level, and therefore the outputof AND gate 9 j will also be at the “H” level, and the “H” level signalwill be input to terminal CI of C element 9 b. Thus, the signal level atterminal RI of the self-synchronous transfer control circuit is changedfrom “L” to “H”, fulfilling the conditions in that C element 9 boperates as in the conventional example, and hence terminal CP of Celement 9 b is raised from “L” level to “H” level.

On the other hand, terminal CO of C element 9 b falls from “H” level to“L” level. The “H” level signal of the output of terminal CP of Celement 9 b sets flip-flop 9 s, so that the “H” level signal is outputfrom terminal FEB of the self-synchronous transfer control circuit viadelay element 9 t. Thereafter, counter 9 f counts up from 0 by a risingsignal of terminal CP of C element 9 b. Counter 9 f outputs the countedresult of “0” from terminal NO, outputting an “H” level signal fromterminal Z of counter 9 f if it corresponds to the number set by inputterminal NUM, and outputting an “L” level signal if there is nocorrespondence.

A case where no correspondence is found between the counted result andthe set number will now be discussed. At that time, the “L” level signalis output from terminal Z of counter 9 f, and is therefore input to ORgate 9 n. As described earlier, AND gate 9 m is masked by the “L” levelsignal of the output from inverter 9 q, so that terminal RI of C element9 a is fixed to the “L” level, and terminal CO of C element 9 a is fixedto “H” level. This makes the output of NAND gate 9 i “H” level, and thusthe output of OR gate 9 n passes through AND gate 9 j as it is.

Therefore, the signal output from terminal CO of C element 9 b is inputto terminal CI of C element 9 b maintaining its level. Likewise,terminal CO of C element 9 a is fixed to “H” level, allowing AND gate 9p to output the signal output from terminal CO of C element 9 b withoutchange of its level from terminal CO of the self-synchronous transfercontrol circuit. Because the “L” level signal is output from terminal COof C element 9 b, the second “L” level signal is output from terminal COof the self-synchronous transfer control circuit. Further, an “L” levelsignal is input to terminal CI of C element 9 b via OR gate 9 n and ANDgate 9 j.

After a certain period of time, an “L” level signal is input to terminalRI of the self-synchronous transfer control circuit, and thus an “L”level signal will be input to terminal RI of C element 9 b. This changesthe signal level of terminal CP of C element 9 b from “H” to “L”, andthat of terminal CO of C element 9 b from “L” to “H”. The “H” levelsignal output from terminal CO of C element 9 b is output from terminalCO of the self-synchronous transfer circuit as the “H” level signal viagate 9 p, while being input to terminal CI of C element 9 b also as the“H” level via OR gate 9 n and AND gate 9 j. When the signal level atterminal RI of the self-synchronous transfer control circuit is changedfrom “L” to “H” after a certain period of time, the second packettransfer is terminated. At that time, terminal FEB outputs an “H” levelsignal, and terminal NO outputs a “0” level signal.

The “H” level signal input from terminal RI of the self-synchronoustransfer control circuit is input to terminal RI of C element 9 b, sothat conditions are matched where C element 9 b operates as in theconventional example, as described in the earlier second packettransfer, the signal level of terminal CP of C element 9 b rising from“L” to “H”, and that of terminal CO of C element 9 b falling from “H”level to “L” level. Counter 9 f counts up from “0” to “1” upon the riseof the signal at terminal CP of C element 9 b, comparing the countedresult with the number set at terminal NUM. The self-synchronoustransfer control circuit compares the number of counting executed bycounter 9 f and the set number input from terminal NUM, repeats theabove operation until they correspond with each other, and keepsoutputting pulse signals from terminal CO of the self-synchronoustransfer control circuit.

A case where the number of counting counted by counter 9 f and the setnumber input from terminal NUM correspond with each other will now bediscussed. At that time, an “H” level signal is output from terminal Zof counter 9 f, and the output of OR gate 9 n is fixed to the “H” level.The “H” level signal of the output of OR gate 9 n is fixed to a statewhere terminal CI of C element 9 b is raised to the “H” level via gate 9j, so that no pulse will be output from C element 9 b. Further, terminalCP of C element 9 b is then fixed to the “H” level, and terminal CO of Celement 9 b is fixed to a state where “L” level is output therefrom.This is the state where the “L” level signal for transferring the lastcopy packet is output from terminal CO of the self-synchronous transfercontrol circuit.

An “L” level signal is input from terminal RI of the self-synchronoustransfer control circuit after a certain period of time, and thus the“L” level signal is input to terminal RI of C element 9 b. C element 9 breceives the signal, changing the level of terminal CP of C element 9 bfrom “H” to “L”, and that of terminal CO of C element 9 b from “L” to“H”. This allows terminal CO of the self-synchronous transfer controlcircuit to output an “H” level signal. Further, D type flip-flop 9 gtakes in a signal at input terminal D synchronously with the rise of thesignal at terminal CP of C element 9 b (the rise via inverter 9 r), andtakes out the signal from output terminal Q of D type flip-flop 9 g.

The input signal of D type flip-flop 9 g is then at “L” level viainverter 9 u, since output signal Z of counter 9 f is at “H” level. Thatis, Q output of D type flip-flop 9 g takes out an “L” level signal, andthe output of inverter 9 q rises to “H” level. This “H” level signal isinput to AND gate 9 m, and the output thereof, which had been fixed to“L” level heretofore, is changed to a signal identical to the signalinput from terminal RI of the self-synchronous transfer control circuit.

Subsequently, terminal CO of the self-synchronous transfer controlcircuit outputs an “H” level signal, so that the “H” level signal isinput to terminal RI of the self-synchronous transfer control circuitafter an additional certain time period. This input signal of “H” levelpasses through AND gate 9 m and is input to terminal RI of C element 9a.

After such a series of operations, the copying operation of theself-synchronous transfer control circuit is terminated. When one pulseis applied to pulse input terminal CI of the self-synchronous transfercontrol circuit from the preceding stage, this circuit can output onepulse from terminal CP, and output any arbitrary number of pulse signalsfrom pulse output terminal CO to the subsequent stage.

Though the copying operation was described with reference to FIG. 2, itis noted that the self-synchronous transfer control circuit continuesthe packet transfer operation as described above, such that, when N isinput as the copying number information, the initial packet transferoperation is performed and thereafter counting is executed from 0, 1, 2,. . . to N. Therefore, N+2 packets are transferred. Conversely, if Ncopies are required, “N−2” will be input as the copying numberinformation.

FIG. 3 is a block diagram showing an example where the self-synchronoustransfer control circuit in the second embodiment of the presentinvention is used for a data transmission device employing a handshakesystem. In the data transmission device shown in FIG. 3,self-synchronous transfer control circuit 13 b shown in FIG. 1 isconnected between C elements 13 a and 13 c, an instruction decoder 13 gis provided between pipeline registers 13 d and 13 e, and a node numbermanipulation circuit 13 h is provided between pipeline registers 13 eand 13 f. The packet data to be input to the data transmission deviceincludes a destination node number, a generation number, an instructioncode and data, as described above with reference to FIG. 12.

When the data transfer from C element 13 a to self-synchronous transfercontrol circuit 13 b is realized, instruction decoder 13 g decodes theinstruction code, providing a CPY flag and copying number informationNUM to self-synchronous transfer control circuit 13 b. Self-synchronoustransfer control circuit 13 b controls the data transfer for C element13 c in the subsequent stage in accordance with the CPY flag and copyingnumber information NUM to be input.

Self-synchronous transfer control circuit 13 b outputs one pulse signalfrom terminal CP when the SEND signal and the ACK signal between thecircuit 13 b and C element 13 c in the subsequent stage are both in the“H” level and when the SEND signal from C element 13 a in the precedingstage rises from “L” level to “H” level. This allows the packet datainput to pipeline register 13 e to be transferred to pipeline register13 f together with the SEND pulse signal from self-synchronous transfercontrol circuit 13 b to C element 13 c.

C element 13 c sends a data transfer enabling signal (ACK signal “H”) toself-synchronous transfer control circuit 13 b when the transfer of thefirst packet to C element (not shown) in the subsequent stage iscompleted. Self-synchronous transfer control circuit 13 b which hasreceived the signal in turn sends the subsequent SEND signal to Celement 13 c, and also the second packet data to pipeline register 13 f.

At that time, self-synchronous transfer control circuit 13 b outputs FEBsignal “H” and NO signal “0”, and node number manipulation circuit 13 hmanipulates the node number using these signals so as to distinguish thesecond packet data from the first packet data. For example, the FEBsignal and the NO signal are added to the node number to distinguish thepackets from each other. Thus, for the “n” th packet, a node number isapplied using the FEB signal and the NO signal such that the packet canbe distinguished the other copy packets. Using a COPYn instruction, theinput of one packet can output a plurality of packets holding the samedata.

FIGS. 4A and 4B contrastively shows programs for an example where fourcopies of packets are made in a conventional example and in theembodiment of the present invention. In the conventional example, onlyup to two copies could be made from one node as shown in FIG. 4A,whereas a plurality of copies can be made by the COPYn instructionaccording to the embodiment of the present invention as shown in FIG.4B, resulting in reduction of the number of executive instructions.

Before describing other examples of the data transmission device usingthe self-synchronous transfer control circuit according to the presentinvention, an efficient processing method of the instruction by whichthe operation result causes an overflow. For example, multiplication oftwo sets of 12-bit data is discussed. In such a case, though theoperation result would be 24-bit data, the data stored in the data fieldas a packet format shown in FIG. 12 is limited to 12 bits, so that theoperation result data of 24 bits could not be stored as one packet only.

In the conventional example described above with reference to FIG. 18,therefore, the operation result data of 24 bits were required to bedivided into higher 12 bits and lower 12 bits for operation. For thispurpose, in the conventional example shown in FIG. 18, the operation wasrealized by executing two instructions such as an instruction outputtinga packet including the higher 12-bit data and an instruction outputtinga packet including the lower 12-bit data by adjusting a shift. Anembodiment for improving this will be described below.

FIG. 5 is a block diagram executing a multiplication instruction by adata transmission device employing a handshake system, including a newself-synchronous transfer control circuit 21 c of the present invention,and FIG. 6 is a circuit diagram showing an example whereself-synchronous transfer control circuit 21 c shown in FIG. 5 isrealized.

In FIG. 5, a transfer control circuit is constituted by C elements 21 aand 21 b, self-synchronous transfer control circuit 21 c, and a Celement 21 d connected in series. Pipeline registers 21 e, 21 f, 21 gand 21 i constitute a data transmission path, in which a multiplier 21 jis connected between pipeline registers 21 e and 21 f, and a shifter 21k, a lower-order extraction circuit 21 l and a copy detection circuit 21m are provided between pipeline registers 21 f and 21 g. Further, amultiplexer 21 h and a node number manipulation circuit 21 n areprovided between pipeline registers 21 g and 21 i. Though the exampleshown in FIG. 1 may be used for self-synchronous transfer controlcircuit 21 c, the self-synchronous transfer control circuit shown inFIG. 6 is used in the present embodiment. N copies were possible in theself-synchronous transfer control circuit shown in FIG. 1, whereas N islimited to 2 in the self-synchronous transfer control circuit shown inFIG. 6, simplifying the configuration compared to the one in FIG. 1.

In FIG. 6, the configuration is similar to that shown in FIG. 1, exceptfor terminal NUM, terminal NO, D type flip-flop 9 e, counter 9 f, ANDgate 9 j, OR gate 9 n and inverter 9 u. Further, FIGS. 7A to 7H aretiming charts showing the operation of the circuit shown in FIG. 6.

The data transmission device shown in FIG. 5 is included in operationunit FP of the data driven processor shown in FIG. 17. The packet to beinput to operation unit FP of the data driven processor stores a pair ofdata (two sets of 12-bit data) to be subjected to the operation. Thepacket including two non-operated data of 12 bits is input to pipelineregister 21 e, the operation is executed by multiplier 21 j, and theoperation result of 24-bit data is temporarily stored in the data fieldof the packet, which is held in pipeline register 21 f. The 24-bit datais output from pipeline register 21 f, and divided into the higher12-bit data and the lower 12-bit data by shifter 21 k and lower-orderextraction circuit 21 l, in accordance with the shift read from theinstruction code, to be output to pipeline register 21 g.

Furthermore, copy flag CPY is read from the instruction code by copydetection circuit 21 m and is provided to self-synchronous transfercontrol circuit 21 c. Self-synchronous transfer control circuit 21 coutputs a CP pulse signal to pipeline register 21 g when the “H” levelsignal indicating the detection of copying is input to terminal CPY,exchanging the SEND signal and the ACK signal with C element 21 d twice,and sends two packets to pipeline register 21 i as a result.

The first packet is output with the “H” level of the FEB signal, whereasthe second packet is output with the “H” level of the FEB signal. Usingthe FEB signal, the node numbers are manipulated by node numbermanipulation circuit 21 n to distinguish the packets from each otherwhile the output of multiplexer 21 h, to which the higher 12-bit dataand the lower 12-bit data of the operation result are input, isswitched.

Thus, the first packet transferred from pipeline register 21 g topipeline register 21 i stores the higher 12 bits of the multiplicationresult, whereas the second packet, in which its node number ismanipulated by, for example, incrementing thereof, stores the lower 12bits of the multiplication result.

FIGS. 8A and 8B contrastively show flow diagrams for the multiplicationbetween two sets of 12-bit data according to a conventional example andthe third embodiment of the present invention.

Conventionally, as shown in FIG. 8A, an NOP instruction was executed tomake two copies required for each of two sets of 12-bit data input froman input port IN1 and an input port IN2. Subsequently, an MULa(multiplication) instruction was executed to output the higher 12 bitsof the multiplication result from an output port OUT1, and an MULbinstruction was executed to output the lower 12 bits of themultiplication result from output port OUT2.

In contrast, an MULc instruction according to an embodiment of thepresent invention multiplies two sets of 12-bit data input from inputports IN1 and IN2 as shown in FIG. 8B, to output the higher 12 bits fromoutput port OUT1 and the lower 12 bits from output port OUT2 as aresult. Thus, the number of the steps for executive instructions hasbeen reduced to a quarter of that in the conventional example, so that asimple calculation indicates that the operation speed four times as fastas that of the conventional case can be expected.

FIGS. 9 to 11 show the fourth embodiment of the present invention. Inparticular, FIG. 9 is a block diagram showing a data driven deviceperforming efficient operation process of three sets of data, FIG. 10 isa circuit diagram of the self-synchronous transfer control circuit shownin FIG. 9, and FIGS. 11A to 11J are timing charts showing the operationof the self-synchronous transfer control circuit shown in FIG. 10.

Two sets of data were handled by one packet in the data transmissiondevice according to the embodiment shown in FIG. 5 as described earlier,whereas in the embodiment shown in FIG. 9, one packet is input toexecute operation for three sets of data, outputting three packetsstoring three operation results.

In FIG. 9, C elements 31 a and 31 b, a self-synchronous transfer controlcircuit 31 c, and C elements 31 d, 31 e and 31 f are connected in seriesas a transfer control circuit. Further, pipeline registers 41 a to 41 fare connected as a data transmission unit, in which an address detectioncircuit 41 g is connected between pipeline registers 41 a and 41 b, acopy detection circuit 41 h is connected between pipeline registers 41 band 41 c, a multiplexer 41 i and a node number manipulation circuit 41 jare connected between pipeline registers 41 c and 41 d, a multiplier 41k is connected between pipeline registers 41 d and 41 e, and a shifter41 l is connected between pipeline registers 41 e and 41 f.

For self-synchronous transfer control circuit 31 c, though a similaroperation result could be obtained by inputting “H” level to terminalCPY and an “H” level signal to terminal NUM in the circuit shown in FIG.1, the self-synchronous transfer control circuit shown in FIG. 10 canbetter simplify the circuit. Thus, the self-synchronous transfer controlcircuit shown in FIG. 10 is provided with a terminal R3 in place ofterminal NUM shown in FIG. 1, a single-bit D type flip-flop 9 w in placeof D type flip-flop 9 e in FIG. 1, and a counter 9 x counting from 0 to2 in place of counter 9 f counting up to N shown in FIG. 1. This resultsin reduction of the scale of the circuit as a self-synchronous transfercircuit compared to the one in FIG. 1. The self-synchronous transfercontrol circuit shown in FIG. 10 operates almost in the same manner asthe circuit shown in FIG. 1.

As shown in FIGS. 11D and 11E, when “H” level signals are input bothfrom terminal CPY and terminal R3, three packet copies are enabled,outputting the first packet when FEB=“L” level and LST=“L” level,outputting the second packet when FEB=“H” level and LST=“L” level, andoutputting the third packet when FEB=“H” level and LST=“H” level, asindicated in FIGS. 11H and 11F.

The data transmission mechanism shown in FIG. 9 is included in operationunit FP of the data driven processor shown in FIG. 17. The packet to beinput to operation unit FP of the data driven processor stores a pair ofdata (two sets of 12-bit data). When this packet is input to pipelineregister 41 a, one of the two sets of data is used for address detectionof a table memory 41 m by address detection circuit 41 g, and the otheris used for the data for multiplication.

The instruction code of the input packet is decoded and a CPY signal anda R3 signal are sent to self-synchronous transfer control circuit 31 cby copy detection circuit 41 h, while the content of table memory 41 mis stored in the packet and held by pipeline register 41 c. If both theCPY signal and the R3 signal are at “H” level, self-synchronous transfercontrol circuit 31 c outputs a CP pulse signal to pipeline register 41 cand exchanges a SEND signal and an ACK signal with C element 31 d threetimes, resulting in output of three packets to pipeline register 41 d.

Using the FEB signal and the LST signal output from self-synchronoustransfer control circuit 31 c, the node numbers of the packets aremanipulated by node number manipulation circuit 41 j to distinguish thepackets from each other, while the output of multiplexer 41 i, to whichhigher-bit data, middle-bit data and lower-bit data of the data readfrom table memory 41 m are input, is switched.

This means that the first packet transmitted from pipeline register 41 cto pipeline register 41 d stores the higher bits of the memory datawithout manipulation of its node number, the second packet ismanipulated for its node number (e.g. the node number+1) and stores themiddle bits of the memory data, and the third packet is manipulated forits node number (e.g. the node number+2) and stores the lower bits ofthe memory data. The respective memory data stored in the three packetsoutput from pipeline register 41 d are multiplied with the data storedin the packets for multiplication by multiplier 41 k, and are stored inpipeline register 41 e. If the multiplied result causes an overflow,adjustment is made by shifter 41 l.

As described above, according to the present embodiment, the input ofone packet allows the operation to be executed for three sets of data,resulting in reduction of the number of the executive instructions.Assuming that 24-bit data is read from table memory 41 m, the operationcan be carried out for three sets of 8-bit data. This can be applied inimage data processing such as RGB (24 bits) to increase the speed of theimage processing.

As has been described above, according to the embodiments of the presentinvention, one data transfer request pulse signal can be received from atransfer control circuit in a preceding stage to output a plurality ofdata request pulse signals to a transfer control circuit in a subsequentstage, enabling several times more efficient data transfer controlcompared to that of the conventional art.

Further, the number of the data request pulse signals for the subsequentstage in the self-synchronous transfer control circuit may be includedin a packet to be input to enable the packet copying as desired.

Moreover, it is possible to make a plurality of copies of packets havingidentical data from one input packet without repeated execution of theNOP instruction, so that the number of the executive instructions can bereduced, and thus the program performance is enhanced several-fold.

Furthermore, a plurality of sets of data can actually be operated byexecuting one instruction, so that the number of the executiveinstructions can be reduced, and thus the program performance isenhanced several-fold.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

1. A self-synchronous transfer control circuit, comprising: a transfercontrol circuit transferring a first pulse applied from a precedingstage to a subsequent stage as a second pulse based on an instructionsignal instructing enabling or disabling a transfer; a pulse controlcircuit receiving one data transfer request pulse signal as said firstpulse from said transfer control circuit in the preceding stage tooutput a plurality of data transfer request pulse signals as said secondpulse to the transfer control circuit in the subsequent stage, and adata number setting means setting the number of data transferred to saidtransfer control circuit in the subsequent stage, wherein the transfercontrol circuit, the transfer control circuit in the preceding stage,and the transfer control circuit in the subsequent stage aresubstantially, similarly configured, and wherein the transfer controlcircuit transferring a first pulse applied from a preceding stage to asubsequent stage as a second pulse is self-synchronous.
 2. Theself-synchronous transfer control circuit according to claim 1, whereinsaid pulse control circuit includes a first logic circuit outputting atransfer enabling pulse signal to said transfer control circuit in thepreceding stage as a third pulse, in response to application of saiddata transfer request pulse signal from said transfer control circuit inthe preceding stage, a second logic circuit outputting data transferrequest pulse signal to said transfer control circuit in the subsequentstage, a storage circuit storing the number of data in response tosetting of the number of data by said data number setting means, a gatecircuit receiving a transfer enabling signal as a fourth pulse from saidtransfer control circuit in the subsequent stage and, a transfer circuitoutputting said transfer request pulse signal from said second logiccircuit by the number of data stored in said storage circuit every timesaid gate circuit receives said transfer enabling signal, in response toapplication of said data transfer request pulse signal to said firstlogic circuit, when said number of data is stored in said storagecircuit.
 3. The self-synchronous transfer control circuit according toclam 2, wherein said pulse control circuit includes a counter circuitcounting the number of times said transfer request pulse signal isoutput, and a disabling circuit comparing the counter output of saidcounter circuit with the number of data stored in said storage circuitto disable the output of said transfer request pulse signal by saidtransfer circuit, in response to correspondence thereof.
 4. The datadriven information processing device of claim 1, wherein the output ofthe plurality of data transfer request pulse signals is a copyingprocess.
 5. A data driven information processing device, using aself-synchronous transfer control circuit receiving one data transferrequest pulse signal indicating request of transfer from a transfercontrol circuit in a preceding stage to output a plurality of transferrequest pulse signals to a transfer control circuit in a subsequentstage, comprising: a data transmission path holding a data packet basedon a pulse signal applied from said self-synchronous transfer controlcircuit; and a data number detection means for detecting the number ofdata based on output packet information set to the data packet held insaid data transmission path, said self-synchronous transfer controlcircuit outputting a transfer request pulse signal corresponding to thenumber of data, in response to detection of the number of data by saiddata number detection means, wherein said data number detection meanstransmits a plurality of data packets different from data packet fromthe data transmission path to a data transmission path in a subseciuentstage, in response to detection of said copying instruction.
 6. The datadriven information processing device according to claim 5, wherein saiddata transmission path holds a data packet including a destination fieldstoring at least destination information, an instruction field storinginstruction information and a data field storing data; and said datanumber detection means transmits, in response to detection that acopying instruction is present in an instruction field included in thedata packet held in said data transmission path, data copied from thedata transmission path in a subsequent stage.
 7. The data driveninformation processing device according to claim 6, wherein a datanumber detection means transmits a plurality of data packets having thesame data as the data in a data field included in the data packet andhaving destination information different from each other, from the datatransmission path to the data transmission path in a subsequent stage,in response to detection of said copying instruction.
 8. The data driveninformation processing device of claim 5, wherein the pulse signal isnot a clock signal.